(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming passivation openings by reflow of photoresist to eliminate protective tape residue in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Ultra Large-Scale Integration (ULSI) devices are assembled into integrated circuit packages using a sequence of processes that occur after the circuit wafers have completed the topside processing. This secondary sequence of processes is typically called the assembly process, or the back-end process of the manufacturing plant.
An important step in the assembly process is a step called backside grind. Large diameter wafers, common in modern ULSI technologies, must be made substantially thick to withstand the rigors of the topside, or device side, processing without breaking. However, the completed circuit die often need to be thinner to facilitate heat transfer and to correct for thermal mismatch in the packaged part. In addition, thick wafers place more demands on the dicing process wherein the wafers are sawed into individual chips. It is therefore necessary to reduce the thickness of the wafers after the topside processing is completed.
The backside grinding process is used to thin the wafers. In the backside grinding process, the wafers are first covered with a protective tape. Then the wafers are positioned, topside down, on a grinding chuck. Material is removed from the backside of the wafer using a grinding process.
Referring now to FIG. 1, a top view of an integrated circuit die 10 is shown. This integrated circuit die 10 comprises one of hundreds or thousands of such circuits on an integrated circuit wafer. Note that a series of bonding pads 14 ring the perimeter of the die 10. These bonding pads are openings in the passivation layer that overlies the surface of the die 10. Each bonding pad 14 represents a location where the integrated circuit package will contact the die using, for example, a wire bond.
Referring now to FIG. 2, a cross section of a bonding pad is shown. The semiconductor substrate 20 is shown as a homogeneous layer for simplicity of illustration. However, in practice, the semiconductor substrate 20 would comprise several layers to create the devices of the circuit. A metal layer 24 overlies the semiconductor substrate 20. A passivation layer 28 overlies the metal layer 24 to electrically isolate and protect the metal layer 24 and the semiconductor substrate 20 from the integrated circuit package.
The bonding pad opening is formed in the passivation layer 28 using a conventional photolithographic sequence. A photoresist layer 32 is first deposited overlying the passivation layer 28. The photoresist layer 32 is exposed and developed to thereby expose the passivation layer 28 in the areas overlying the metal layer 24 where the bonding pads are planned. The passivation layer 28 is etched through to form the bonding pads. Sharp edges 36 are formed in the passivation layer 28.
Referring now to FIG. 3, after the topside processing is complete, the topside of integrated circuit wafer is covered with a protected tape 40 and 44. The protective tape 40 and 44 is typically a laminate material comprising an adhesive film 40 and a tape layer 44. The tape layer 44 protects the wafer from damage during the backside grinding operation.
Referring now to FIG. 4, after the backside grinding operation has thinned the semiconductor substrate 20, the tape layer 44 is removed. A problem in the method of the prior art is then illustrated. The relatively sharp edges of the bonding pad opening can sheer away a portion of the adhesive film and cause an adhesive residue 48 to remain after the protective tape is removed. This adhesive residue 48 can cause wire bonding problems that reduce reliability and product yield.
Referring now to FIG. 5, one prior art solution to this problem is to create a stair step profile 52 on the bonding pad opening. In this method, a two-step etching process is used whereby an undercut of the passivation layer 28 is achieved. However, this method is not effective in preventing tape adhesive residue when the bonding pad number exceeds 35,000. In addition, two etch machines and additional cycle time are required to create the stair-step profile.
Several prior art inventions describe methods to prevent adhesive residue, to form bonding pads, or to reflow photoresist. U.S. Pat. No. 5,731,243 to Peng et al teaches a method to reduce protective tape adhesive contamination. The photoresist layer used to define the bonding pad openings is removed after the pad etch. A special cleaning step is added to remove any residual polymer. The inclusion of the special cleaning step reduces adhesive residue after the protective tape is removed. U.S. Pat. No. 6,060,378 to Rolfson discloses a method to form bonding pads with improved reliability. The passivation layer is etched to create pad openings. U.S. Pat. No. 6,025,275 to Efland et al discloses a method to form thick plated copper interconnects. A photoresist with a reflow step is used between the etch of the bondable metal layer and etch of the seed layer. By reflowing the photoresist layer, the sidewalls of the bondable metal layer are covered and protected from undercutting during the seed layer etch. U.S. Pat. No. 5,063,655 to Lamey et al teaches a method to integrate the driver pulse circuitry and the resistors of an ink jet printer onto the printer head. A photoresist with reflow step is used to create a gradually sloping contact opening. The sloping contact is used to connect the metal layer and the resistor layer and prevents cracking of the metal layer.